In logic devices such as programmable logic arrays and programmable logic devices, line drivers arc frequently used to drive signals on shared signal lines. In some instances, it is desirable for a line driver to drive a signal on one line and provide the complement of the signal on a second line. This is particularly useful in logic arrays in which each input signal is provided in inverted and noninverted forms for potential connection to the inputs of one or more logic gates.
In addition, it is useful for the line drivers in a logic array to respond to a global enable signal, which can disable all line drivers to prevent large power transients and noise caused by the unwanted switching of line drivers. The line drivers may therefore each include a pass gate which only provides a conduction path from the line driver input to the driving circuitry of the line driver if the line driver is enabled by the enable signal. However, when a line driver is enabled, the pass gate of the line driver may cause significant delay in the switching of the line driver input signal.